Praveen Kumar
M Tech (Microelectronics)
Indian Institute of Technology, Bombay
Maharashtra; India-400 076
Internet: http://www.geocities.com/binu_praveen
Email: binu_praveen@yahoo.com
Current Address:
C/O Mr Srinath Singh
House #10, SBI Colony M P Nagar-II, Bhopal
Madhya Pradesh India - 462 016
Telephone:+91 755 429 2514 (H)
+91 755 276 2524 (O)
Permanent Address:
S/O Dr. P. C. Sah
Jhanjahrpur Purani Bazar
Madhubani
Bihar, India - 847 404
Telephone: +91 627 322 3573
+91 930 401 9056
Objective:
To secure an entry level position as "Design Engineer" in "VLSI
Design Industry"
with the responsibility of design and development.
VLSI Design, System Hardware Design, Modern Elecronic Design Techniques,
Computer-Aided Analysis and Design, Hardware Description Language, Digital
Signal Processing, Physical
Electronics, Physics of Transistor, VLSI Technology and Microelectronics Lab.
Implementation of Interrupt Controller Unit of 80186 using
Verilog.
Implementation of ALU (16 bit) using Verilog.
Implementation of Single slope ADC, Triangular wave and Square
wave generator using SPICE.
Design of two stage CMOS OP-AMP for a given specifications,
using SPICE.
Implementation of MOV instruction of 8085 and IEEE GPIB source
and acceptor handshake using IRSIM.
Layout of circuit of MOV instruction of 8085 (implemented in
IRSIM) using Magic.
Design of complete CMOS process for 70 nm technology using
SUPREM-IV.
Design of NMOS for 250 nm technology in TSUPREM-IV and study of
Id-Vd, Id-Vg, VT roll-off, and subthreshold swing with respect to
different channel implant depth were done using MIDICI.
Implementation of BFS, DFS and MST using C++.
Design of Bandgap Reference.*
* Not a course project, but designed out of curiosity.
Achievements:
R. S. Narayanan Scholarship (1998-1999)
Prof. Vidya Bhusan Scholarship (1999-2000)
Prof. Neeraj Srivastave Award (2000)
GATE 2000 : Scored 98.92 percentile in the Graduate Aptitude Test
in Enginnering (Physics) with an all India rank of 14.
Qualified in national level junior reserch fellowship/lecturership
eligibility test in Physics conducted by CSIR, India in the year 2000.
Fellow of Tata Consultancy Services, at I I T Bombay, July 2000 - January 2002
Tools & Packages Learnt:
VLSI Design Tools/simulators:
Xilinx(VHDL/Verilog)*, SPICE, SABER, IRSIM, MAGIC
Device and Process Simulators:
MIDICI, PISCES, TSUPREM-IV, SUPREM-IV
Software Experience:
Worked on Solaris, Linux/Unix, Windows platform
Familier with C, C++, HTML
* I am familier with both VHDL and Verilog.
Personal:
Date of Birth : March 1st, 1978
Sex : Male
Marital Status: Single
Citizenship : Indian
Hobbies : Reading books, Listening Indian Music
Interest : Deep interest in learning issues involved with RF Design